In the area of digital systems, the task of accommodating increasing bus traffic continues to pose a challenge. The primary bottle-neck in most bus transactions appears to be the system bus. The system bus is a bottle-neck primarily because many devices share the same bus and must contend for its resources.
The PCI bus is a high performance, 32-bit or 64-bit bus with multiplexed address and data lines which can accommodate multiple high performance peripherals. The PCI Bus supports burst modes in which a bus transaction may involve an address phase followed by one or more data phases in tandem with a command phase followed by one or more byte enable phases. As such, an external device may require the use of the bus for multiple clock cycles during a bus transaction which can exacerbate bottle-neck problems associated with a system bus. Reference is now made to FIG. 1 which illustrates an overview of a computer system that utilizes the PCI bus. In FIG. 1, computer system 100 comprises host CPU 101, host memory 102, peripheral hardware controller 103, and bridge device 105. Peripheral hardware controller 103 is coupled to host CPU 101 and host memory 102 through PCI bus 104. More particularly, peripheral hardware controller 103 provides an interface between PCI bus 104 and external devices such as disk drivers, display monitors, parallel data port, local area network, wide area network, or the like.
In general, host CPU 101 and external devices may take turns controlling PCI bus 104 in carrying out transactions such as read and write transactions. While a device which takes control of PCI bus 104 to initiate the transaction is known as a "bus master" device, a device at the other end of the transaction is known as a "bus target" (or "slave") device. Information that are involved in bus transactions between devices include data, address, commands, byte enables, and identification of bus master and bus target device.
While a bus may be synchronous or asynchronous, PCI bus is a synchronous bus. In other words, information flowing from the bus master device to the target device and vice versa are synchronized to a system clock such that a bus transaction must take place in an integral number of synchronized clock cycles. In carrying out bus transactions, bus protocols must be followed. These protocols consists mainly of bus mastership, requests for read or write transactions, and acknowledgment of such requests. PCI bus protocols can be found in "The PCI Local Bus Specification Rev 2.1", published by the PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214 and incorporated herein by reference.
When host CPU 101 performs a write transaction to a device connected to the PCI bus 104 such as peripheral hardware controller 103, the write transaction is considered complete when data information is sent to the device. In general, when peripheral hardware controller 103 receives the data from host CPU 101, the data is first stored in a temporary buffer such as a first-in-first-out (FIFO) buffer before being transferred to a final destination such as a local memory inside peripheral hardware controller 103. The FIFO buffer is used to prevent data loss or corruption that may occur, for example, when the local memory is full or the bus connecting the local memory to the buffer is temporarily busy and new data is coming in from host CPU 101. However, data loss can still occur, for example, if new data is coming into a full FIFO buffer and the FIFO buffer can not empty its content into the local memory because the local bus is temporarily busy. As a result, the data may be corrupted before reaching the local memory.
To ensure that the data retrieved from the final destination is not corrupted, a software driver is used in the Prior Art to determine whether the data has actually reached its intended final destination and therefore not corrupted. Referring now to FIG. 2 illustrating a flow chart of an exemplary software driver used to determine whether data has actually reached its intended final destination. Suppose that host CPU 101 performs a write transaction of the value 100 into address 10 of the local memory inside peripheral hardware controller 103. Further suppose that the data to be stored at memory address 10 is processed through a logical or arithmetical operator before reaching its final destination at memory address at 10. Immediately following this write transaction, host CPU 101 requests and gains control of the PCI bus to execute the software driver stored in memory 102. In step 201, a known value is written into address 20 of the local memory (step 201). The content of address 20 is retrieved in step 202. Because the write transaction to address 20 occurs after the write transaction to address 10, if the content of address 20 matches the known value following step 203, it can be safely assumed that the value of 100 has actually reached the final destination (i.e., address 10 of the local memory). Hence, a read transaction of address 10 is performed (step 204). Otherwise, go back to read address 20 again. As shown in FIG. 2, at least four instructions must be executed before a determination can be made. At a few clock cycles per instructions, using a software driver to determine whether the data actually reaches the final destination is very inefficient. The inefficiency is even greater if the clock cycles needed for bus arbitration are included.
Hence, there is a need for an apparatus, system, and method to efficiently determine whether data actually reached the final destination without being corrupted.